By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit layout includes the contribution of 18 tutorials of the seventeenth workshop on Advances in Analog Circuit layout. every one half discusses a particular to-date subject on new and worthy layout rules within the zone of analog circuit layout. each one half is gifted via six specialists in that box and cutting-edge info is shared and overviewed. This e-book is quantity 17 during this winning sequence of Analog Circuit layout.
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Extra info for Analog Circuit Design: High-speed Clock and Data Recovery, High-performance Amplifiers, Power Management
G. Wilson, W. Rhee, and B. Song, “Integrated RF receiver front ends and frequency synthesizers for wireless,” Emerging Technologies: Designing Low Power Digital Systems, International Symp. on Circuits and Systems, May 1996. V. Reinhardt, “Spur reduction techniques in direct digital synthesizers,” in Proceedings of 47th Frequency Control Symposium, Oct. 1993, pp. 230241. W. Rhee and A. Ali, “An on-chip phase-compensation technique in fractional-N frequency synthesis,” in IEEE Proceedings of ISCAS, vol.
Perrott, “Techniques for High Data Rate Modulation and Low 49 Power Operation of Fractional-N Frequency Synthesizers with Noise Shaping”, PhD Thesis, MIT, 1997. be Abstract Does fractional-N synthesis offer the way out for monolithic CMOS integration of high-quality transceivers? e. the spectral purity, integratability and agility. Linear system theory is applied to uncover the fundamental bandwidth limitations imposed by the noise in typical PLLs. Practice however proves the linear approach inaccurate.
Modula- Fractional-N Synthesis: Linear Analysis To model the impact of on the spectral purity of the synthesizer, a linear-time-invariant (LTI) PLL model is employed, with the quantization noise as an additive noise source at the prescaler output. The prescaler with can be looked upon as a digital-to-phase (D/P) converter. Every reference cycle, the prescaler subtracts rad from its input signal, with determined by the modulator output. As guinea pigs for the analysis, a 3rdorder MASH modulator and the 3rd-order, single-loop, multi-bit modulator of Fig.